The 68040 processor. 2. Memory design and chip

1 June 1990

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro

Vol. 10 (3) , 22-35
https://doi.org/10.1109/40.56323

Abstract

For pt.1 see ibid., February (1990). The memory subsystem, the external bus, chip and board testing, and design-verification methods for the 68040, a third-generation, full-32-bit microprocessor in the Motorola 68000 family, are discussed. The internal caches and memory management are examined at length. The external bus protocol, arbitration, snooping, and timing specifications are addressed. The MOVE16 instruction, which moves a cache line from one address (which may reside in the data cache) to another address outside the cache is described. User testing, based on dedicated test logic that is fully compliant with the IEEE 1149.1 standard, and factory testing, for which the processor employs structured design techniques for random logic and special test modes for embedded arrays, are examined. The use of top-down design and a hierarchical method of design verification is discussed.

Keywords

This publication has 6 references indexed in Scilit:

MIS: A Multiple-Level Logic Optimization System
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
Cache memory performance in a unix enviroment
ACM SIGARCH Computer Architecture News, 1986
Cache evaluation and the impact of workload choice
ACM SIGARCH Computer Architecture News, 1985
Instruction Cache Replacement Policies and Organizations
IEEE Transactions on Computers, 1985
The Motorola MC68020
IEEE Micro, 1984
Logic Minimization Algorithms for VLSI Synthesis
Published by Springer Nature ,1984