2V low-power bipolar logic

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Abstract
The scale of integration, especially in bipolar technologies, is mainly limited by the high power dissipation of logic gates. If 5 W is the overall limit, a single gate should consume less then 0.5 mW for 10 k complexity. Due to the small parasitic capacitances of modern submicron silicon technologies intrinsic propagation delay times of about 100 ps can be achieved even in low-power-ranges. However, in high-density integrated circuits, a significant fraction of the gates is loaded by long connection lines. Line lengths up to a few mm are inevitable, resulting in load capacitances of hundreds of fF up to about 1 pF. In these cases, powered-down ECL or CML gates lose their high-speed advantage. This paper describes a 2V circuit that allows high drive capability even at very low power consumption.

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