Three dimensional IC for high performance image signal processor

1 January 1987

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1987.191362

Abstract

The three-dimensional (3-D) image processing test IC designed with parallel processing architecture is fabricated. The device consists of 5-by-5 array of photosensors, 2-bit CMOS A-to-D converters, 40 arithmetic logic units (ALU) and shiftregisters arranged in a 3-layer structure. The total operation from photosensor on top layer to ALU on bottom layer is confirmed, and it is also demonstrated the feasibility of very high speed system operation with the implement of parallel processing. This device gives a clear image of the intelligent image processor on one chip as a future application of 3-D ICs.

Keywords

SIGNAL PROCESSING
THREE-DIMENSIONAL INTEGRATED CIRCUITS
SILICON
CRYSTALLIZATION
IMAGE PROCESSING
PARALLEL PROCESSING
LOGIC ARRAYS
ARITHMETIC
CMOS LOGIC CIRCUITS
SIGNAL DESIGN

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