Finite state machine trace analysis program

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Abstract
We describe a novel approach to verify finite state machines. We describe the finite stale machine (FSM) trace analysis tool that analyzes run time traces of finite state machines while the FSMs are being simulated and reports to the user information about state transitions and arcs traversed. During the flow this tool creates a separate Verilog monitor routine for each FSM in the design and these monitor routines print out the necessary information. Therefore, this tool is useful for all Verilog FSM designers because they do not have to include arc monitoring in their Verilog code when writing the FSMs. The FSM analysis tool is integrated well into the Verilog/Synopsys design methodology.

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