A formal approach towards electrical verification of synchronous MOS circuits
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- Combinational static CMOS networksIntegration, 1987
- Derivation of Signal Flow Direction in MOS VLSIIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A Switch-Level Timing Verifier for Digital MOS VLSIIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- DIALOG: An Expert Debugging System for MOSVLSI DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay ModelingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- NORA: a racefree dynamic CMOS technique for pipelined logic structuresIEEE Journal of Solid-State Circuits, 1983