Dynamic logic CMOS circuits
- 1 April 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 19 (2) , 263-266
- https://doi.org/10.1109/jssc.1984.1052129
Abstract
A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.Keywords
This publication has 2 references indexed in Scilit:
- High-speed compact circuits with CMOSIEEE Journal of Solid-State Circuits, 1982
- A CMOS microprocessor for telecommunications applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977