Using an SCR as ESD protection without latch-up danger

This publication has 3 references indexed in Scilit:

• A low-voltage triggering SCR for on-chip ESD protection at output and input pads
  IEEE Electron Device Letters, 1991
• Direct evidence supporting the premises of a two-dimensional diode model for the parasitic thyristor in CMOS circuits built on thin epi
  IEEE Electron Device Letters, 1988
• An analytic model of holding voltage for latch-up in epitaxial CMOS
  IEEE Electron Device Letters, 1987