Transistor Level Test Generation for MOS Circuits

1 January 1985

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 825-828
https://doi.org/10.1109/dac.1985.1586046

Abstract

Due to inaccuracies in gate level models of VLSI digital circuits, current practice is to use transistor level simulators to analyze VLSI digital circuits. The inaccuracies of gate level models are even more severe when faults in digital circuits are considered. For this reason, recently several researchers have proposed the use of test pattern generation from digital circuits described at the transistor level. In this paper an efficient test pattern generation procedure for digital circuits described at the transistor level is given.

Keywords

CIRCUIT TESTING
MOSFETS
CIRCUIT FAULTS
LOGIC TESTING
FETS
DIGITAL CIRCUITS
VERY LARGE SCALE INTEGRATION
CMOS TECHNOLOGY
LOGIC CIRCUITS
ELECTRICAL FAULT DETECTION

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