Matrix synthesis of high-speed logic
- 1 March 1959
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Transactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics
- Vol. 78 (1) , 4-8
- https://doi.org/10.1109/tce.1959.6372946
Abstract
The object of this paper is to describe a method for synthesizing function matrices from logical conditions and for detecting redundancy prior to designing the network. Accordingly the paper discusses the following: 1. the definition of function matrices and logical operations; 2. the expansion of logical functions in view of additional logical conditions imposed by another variable; and 3. minimization routines.Keywords
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