Effects of Processing on Characteristics of 10–15 nm Thermally Grown SiO2 Films

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Abstract
Thin uniform films, 10–15 nm in thickness, were grown at 800°C in wet ambients. Good dielectric breakdown distribution was observed for films as thin as 10 nm. An barrier height of was obtained for these thin films. The presence of positive charge around the electrode, induced by processing, was found to cause abnormal capacitance‐voltage (C‐V) traces and erroneous results on measurements of minority carrier lifetime by the pulse C‐V technique. Four types of current‐voltage (I‐V) behavior were observed. The generation of traps at high fields was found to be a defect related behavior. A degradation of breakdown distribution for thin films was observed after these films were either dipped in a solution containing and , or subjected to excessive annealing. For annealed polycrystalline silicon structures, an upward grain growth was found, and a pile‐up of phosphorus at the interface was detected.

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