Pulsewidth measurements using an integrated pulse shrinking delay line
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A simple means for measuring pulse widths with nanosecond resolution is presented. The method is based on the use of a fully integrated delay line of CMOS gates having different rise and fall delays. The width of the pulse is decreased by each gate, and the vanishing point of the pulse is detected. Results showing a resolution of 2-3 ns are presented.Keywords
This publication has 4 references indexed in Scilit:
- Time interval measurements using integrated tapped CMOS delay linesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- ECL and CMOS ASICs for time-to-digital conversionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- CMOS ASIC devices for the measurement of short time intervalsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- TMC-a CMOS time to digital converter VLSIIEEE Transactions on Nuclear Science, 1989