Analog Versus Digital Control of a Clock Synchronizer for 3 gb/s Data with 3.ov Differential Ecl

This publication has 2 references indexed in Scilit:

• PLL design for a 500 MB/s interface
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1993
• Continuously variable gigahertz phase-shifter IC covering more than one frequency decade
  IEEE Journal of Solid-State Circuits, 1992