Architectures For Focal Plane Image Processing

Publisher Website
Google Scholar
Abstract
Architectures for focal plane image processing are discussed. On-chip image preprocessing for solid-state imagers using analog CCD circuits is described for low, medium, and high density detector arrays. A spatially parallel architecture for low density, high throughput applications is described. For sparse illumination or event detection, a content-addressable architecture is proposed. A new pipelined vector pixel processor architecture for medium density infrared staring focal plane arrays is described. Neighborhood reconstruction during serial readout of high density TV-quality imagers for a pixel processor is considered using delay and analog frame memory techniques. The potential of on-chip read/write analog frame memory for image transformation and frame-to-frame processing is discussed.

This publication has 0 references indexed in Scilit: