A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme

Publisher Website

23 December 2002

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 126-127
https://doi.org/10.1109/vlsic.1996.507740

Abstract

No abstract available

Keywords

This publication has 0 references indexed in Scilit: