On static compaction of test sequences for synchronous sequential circuits

1 January 1996

conference paper
Published by Association for Computing Machinery (ACM)

p. 215-220
https://doi.org/10.1145/240518.240558

Abstract

We propose three static compaction techniques for test sequences of synchronous sequential circuits. We apply the proposed tech- niques to test sequences generated for benchmark circuits by var- ious test generation procedures. The results show that the test sequences generated by all the test generation procedures consid- ered can be significantly compacted. The compacted sequences thus have shorter test application times and smaller memory requirements. As a by-product, the fault coverage is sometimes increased as well. More importantly, the ability to significantly reduce the length of the test sequences indicates that it may be possible to reduce test generation time if superfluous input vec- tors are not generated.

Keywords

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