Efficient modular design of m -out-of-2 m TSC checkers, for m =2 ^K −1, K >2

7 November 1985

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 21 (23) , 1083-1084
https://doi.org/10.1049/el:19850769

Abstract

A very efficient modular design method for m-out-of-2m TSC checkers, for m=2^K−1, is described. The checkers are designed using full-adder modules and TSC two-rail code checker modules only. Comparisons are made of the number of MOS transistors required and the size of the test set. The low transistor count and the modular structure of the design favours its VLSI implementation.

Keywords

FULL-ADDER MODULES
EFFICIENT MODULAR DESIGN METHOD
VLSI IMPLEMENTATIONS
LOW TRANSISTOR COUNT
TSC MODULE CHECKER MODULES
M-OUT-OF-2 M TSC CHECKERS
MOS TRANSISTORS

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Efficient modular design of m -out-of-2 m TSC checkers, for m =2 K −1, K >2

Abstract

Keywords

Efficient modular design of m -out-of-2 m TSC checkers, for m =2 ^K −1, K >2