A Multiple Media Delay Simulator for MOS LSI Circuits

1 January 1983

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 279-285
https://doi.org/10.1109/dac.1983.1585663

Abstract

This paper concerns an accurate delay modeling of MOS gates at the logic level. The model takes account of the effects of not only the loading capacitance but also the slope of the input waveform. A logic simulator which uses multiple rise/fall delays based on the model is described. Some experimental results are also presented.

Keywords

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