A fully planarized 0.25 μm CMOS technology for 256 Mbit DRAM and beyond

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 15-16
https://doi.org/10.1109/vlsit.1995.520837

Abstract

Results are presented for a fully planarized 0.25 /spl mu/m technology using a trench storage capacitor known as the "BEST" cell. In order to achieve a wide process window for fine patterning, a comprehensive global planarization scheme utilizing chemical mechanical polishing (CMP) is employed. This scheme permits two levels of wiring at a minimum contacted pitch of 0.55 /spl mu/m and allows simplification of other processes related to the gate electrode and borderless array bitline contact. The technology has been exercised to fabricate a 256 Mb DRAM and is extendable to the 1 Gb generation by incremental technology scaling.

Keywords

CMOS TECHNOLOGY
RANDOM ACCESS MEMORY
CAPACITORS
WIRING
PLANARIZATION
ELECTRODES
CHEMICAL TECHNOLOGY
FOCUSING
LITHOGRAPHY
ALUMINUM

This publication has 0 references indexed in Scilit: