A Deductive Method for Simulating Faults in Logic Circuits

1 May 1972

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-21 (5) , 464-471
https://doi.org/10.1109/t-c.1972.223542

Abstract

A deductive method of fault simulation is described, which "deduces" the faults defected by a test at the same time that it simulates explicitly only the good behavior of logic circuit. For large logic circuits (at least several thousand gates) it is expected to be faster than "parallel" fault simulators, but uses much more computer memory than do parallel simulators.

Keywords

This publication has 6 references indexed in Scilit:

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IEEE Transactions on Computers, 1970
High-speed fault simulation for UNIVAC 1107 computer system
Published by Association for Computing Machinery (ACM) ,1968
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IEEE Transactions on Electronic Computers, 1967
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