High-speed VLSI architectures for soft-output Viterbi decoding
- 2 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 373-384
- https://doi.org/10.1109/asap.1992.218558
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Generalized trace back techniques for survivor memory management in the Viterbi algorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An area-efficient path memory structure for VLSI implementation of high speed Viterbi decodersIntegration, 1991
- Wireless digital communication: a view based on three lessons learnedIEEE Communications Magazine, 1991
- Truncation length for Viterbi decodingIEEE Transactions on Communications, 1991
- High-speed parallel Viterbi decoding: algorithm and VLSI-architectureIEEE Communications Magazine, 1991
- Memory Management in a Viterbi DecoderIEEE Transactions on Communications, 1981
- Error-Correction Coding for Digital CommunicationsPublished by Springer Nature ,1981
- Truncation Error Probability in Viterbi DecodingIEEE Transactions on Communications, 1977
- The viterbi algorithmProceedings of the IEEE, 1973
- A Mathematical Theory of CommunicationBell System Technical Journal, 1948