The Convex C240 architecture
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A description is given of the C240, a tightly coupled, shared memory, parallel multiprocessor that supports up to 40-ns ECL/CMOS Cray-like processors. It is managed by a fully semaphored Unix operating system and can support up to 4 Gb of directly addressable physical memory. Convex proprietary compiler technology provides automatic vectorization and parallelization for Fortran, C and Ada. The allocation of parallel threads to physical processors is managed by ASAP (automatic self-allocating processors), which dynamically allocates and deallocates parallel threads to the processors.Keywords
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