Simulated‐annealing‐based optimization of coefficient and data word‐lengths in digital filters

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Abstract
The accurate characterization of worst‐case limit‐cycle behaviour and other finite word‐length effects in digital filters constitutes a challenging and important optimization application. Indeed, for a chip implementation this can lead to a significant reduction in the signal word‐length and hence to considerable savings in terms of the final chip area. This paper describes a new and accurate method for this investigation which is based on a simulated annealing procedure with a general scope. Novel methods for dynamically and efficiently updating the essential parameters of the annealing schedule keep the required CPU times reasonable.The quality of the results obtained with our optimization routine and the general applicability of our approach are further substantiated with some promising results for the quantization of coefficients in arbitrary digital filters.