UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect

25 June 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 64-65
https://doi.org/10.1109/vlsit.2002.1015389

Abstract

UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHP, HP, MP, over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the various performance requirements, multi-V/sub TH/, multi-thickness gate-oxide processes and low-leakage gate dielectric are incorporated in the FEOL. To suppress RC increase compared to the previous generation, low-k (k/sub eff/=3.1) interlayer dielectric and Cu dual damascene interconnects are incorporated in the BEOL.

Keywords

CMOS TECHNOLOGY
RANDOM ACCESS MEMORY
STABILITY
MOS DEVICES
DIELECTRICS
TRANSISTORS
CONTACT RESISTANCE
ULTRA LARGE SCALE INTEGRATION
NATIONAL ELECTRIC CODE
APPROPRIATE TECHNOLOGY

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