A high performance 16-Mb DRAM technology
- 1 January 1990
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A high performance 16-Mb DRAM technology is presented. The key issues that must be considered to achieve high yield and reduced cost are described. Technology elements include: deep trench capacitor node with thick oxide collar for improved packing density, variable-size shallow trench isolation (STI) for device performance and ease of integration, polysilicon surface strap to connect the capacitor node to the transfer device, and smoothed dep/etched phosphosilicate glass (PSG) passivation. The application of the above technology elements in conjunction with the MINT cell structure makes it possible to achieve a DRAM cell size of 4.13 μm2, using six 0.5-μm critical-dimension and 0.2-μm overlay lithography levels. Up to ten sequential process steps are performed in a single cluster. A 50-ns access time has been demonstratedKeywords
This publication has 4 references indexed in Scilit:
- A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A variable-stress shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Planarization of ULSI Topography over Variable Pattern DensitiesJournal of the Electrochemical Society, 1991
- A 45-ns 16-Mbit DRAM with triple-well structureIEEE Journal of Solid-State Circuits, 1989