A General Purpose FASTBUS Interface Chipset

1 January 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 32 (1) , 305-308
https://doi.org/10.1109/TNS.1985.4336844

Abstract

A design concept is presented for a set of semicustom integrated circuits which will interface a master or slave module to a FASTBUS segment. These devices will perform master arbitration, address recognition, handshaking, data pipe-lining and many other standard FASTBUS protocol tasks. Gate arrays are used to implement designs which would require one hundred or more normal integrated circuits, thus greatly reducing the area of a FASTBUS printed circuit board needed for the interface.

Keywords

FASTBUS
MASTER-SLAVE
TIMING
PROTOCOLS
PRINTED CIRCUITS
INTEGRATED CIRCUIT INTERCONNECTIONS
BROADCASTING
APPLICATION SPECIFIC INTEGRATED CIRCUITS
INTEGRATED CIRCUIT PACKAGING
CAMAC

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