Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB(R)
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We present a compiler that takes high level algorithms described in MATLAB and generates an optimized hardware for an FPGA with external memory. A framework is described to detect and exploit opportunities to pipeline loops in an optimal way. Effectiveness of the framework is demonstrated by synthesizing some image and signal processing applications. Starting from the MATLAB description of the applications, hardware is synthesized that runs on a Xilinx XC4028. The synthesized designs are equivalent to manually optimized designs in performance.Keywords
This publication has 5 references indexed in Scilit:
- Pipeline vectorization for reconfigurable systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- FPGA hardware synthesis from MATLABPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLABPublished by Association for Computing Machinery (ACM) ,2000
- Using general-purpose programming languages for FPGA designPublished by Association for Computing Machinery (ACM) ,2000
- Hardware synthesis from C/C++ modelsPublished by Association for Computing Machinery (ACM) ,1999