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A statistical modeling approach for simulation of MOS VLSI circuit designs
Home
Publications
A statistical modeling approach for simulation of MOS VLSI circuit designs
A statistical modeling approach for simulation of MOS VLSI circuit designs
NH
N. Herr
N. Herr
BG
B. Garbs
B. Garbs
JB
J.J. Barnes
J.J. Barnes
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1 January 1982
proceedings article
Published by
Institute of Electrical and Electronics Engineers (IEEE)
https://doi.org/10.1109/iedm.1982.190276
Abstract
No abstract available
Keywords
VERY LARGE SCALE INTEGRATION
PROCESS VARIATION
STATISTICAL DISTRIBUTIONS
SEMICONDUCTOR DEVICE MODELING
STATISTICAL MODEL
STATISTICAL ANALYSIS
PRODUCTION
CHIP
STATISTICAL DISTRIBUTION
Cited
Cited by 2 articles
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