Abstract
A generic iterative model is presented for a wide variety of artificial neural networks (ANNs): single-layer feedback networks, multilayer feed-forward networks, hierarchical competitive networks, and hidden Markov models. Unifying mathematical formulations are provided for both the retrieving and learning phases of ANNs. Based on the unifying mathematical formulation, a programmable universal ring systolic array is derived for both phases. It maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. Hardware implementation for the processing units based on CORDIC techniques is discussed.<>