High-speed binary multiplier
- 20 May 1971
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 7 (10) , 277-278
- https://doi.org/10.1049/el:19710190
Abstract
A multiplier is described which uses a ‘tree’ of adders to add the partial products, resulting in a considerable increase in speed when the adders have a carry-propagation delay per bit which is appreciably less than the addition delay.Keywords
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