Dynamic noise margins of MOS logic gates

Publisher Website

13 January 2003

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iscas.1989.100557

Abstract

No abstract available

This publication has 2 references indexed in Scilit:

Delay-time evaluation in ED MOS logic LSI
IEEE Journal of Solid-State Circuits, 1986
Delay-Time Modeling for ED MOS Logic LSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983