A Stud-bump-bonding Technique For High Density Multi-chip-module

• 24 August 2005
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• p. 362-365
• https://doi.org/10.1109/iemt.1993.639807

Abstract

Keywords

• BONDING
• GOLD
• LARGE SCALE INTEGRATION
• ELECTRODES
• CERAMICS
• CONDUCTIVE ADHESIVES
• WIRE
• STRESS
• PACKAGING
• ARTIFICIAL INTELLIGENCE