A 64b 4-issue out-of-order execution RISC processor

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 170-171
https://doi.org/10.1109/isscc.1995.535508

Abstract

This processor is the first implementation of the SPARC V9 64b instruction set architecture and has an estimated performance exceeding 256 SPECint92 and 330 SPECfp92 at 154 MHz. The R1 processor consists of one CPU chip, one memory management unit (MMU), four cache chips, and one clock chip mounted on a ceramic multi-chip module (MCM). The processor utilizes superscalar instruction issue, register renaming, and data flow execution to exploit instruction-level parallelism.

Keywords

OUT OF ORDER
REDUCED INSTRUCTION SET COMPUTING
MEMORY MANAGEMENT
COMPUTER AIDED INSTRUCTION
COMPUTER ARCHITECTURE
CLOCKS
CERAMICS
REGISTERS
PARALLEL PROCESSING
PACKAGING

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