A 920 gate DSA MOS masterslice
- 1 October 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (5) , 536-541
- https://doi.org/10.1109/JSSC.1978.1051096
Abstract
A DSA MOS (diffusion self-aligned MOS) masterslice circuit with up to 920 gates and a delay of 3 ns per gate has been developed for random logic computer circuits, utilizing the performance and economical advantages of the LSI masterslice approach. To attain high packing density and high speed with conventional design rules, the DSA MOSFET technology has been used for the basic device. The chip comprises 50 by 16 gate cells and 116 input/output buffers. This LSI chip is two to three times better than bipolar S-TTL in packing density and is comparable in propagation delay time. As an example of an LSI device obtained through customized metallization, an 8 bit ALU is described which has an average delay time of 3 ns and a power dissipation of 3 W.Keywords
This publication has 3 references indexed in Scilit:
- A 920 gate masterslicePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978
- Invited: DSA MOS Transistor and Its Integrated CircuitJapanese Journal of Applied Physics, 1977
- Fully ion implanted 4096-bit high speed DSA MOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977