CPAC—Concurrent Processor Architecture for Control
- 1 February 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-34 (2) , 163-169
- https://doi.org/10.1109/TC.1985.1676553
Abstract
We describe a computer architecture for implementing real-time controllers. The concurrent processor architecture for control (CPAC) is optimized for computing the state transitions of a controller. While general-purpose computers are optimized for data manipulation, CPAC is optimized for state manipulation since the states of a controller and the rules governing state transitions constitute a complete high-level description of a controller implementation. The CPAC architecture characterizes a controller in terms of the sets of continuous and discrete states of the system and-logically as well as physically separates the two sets. This dichotomy results in a simpler specification of the rules for state transitions.Keywords
This publication has 9 references indexed in Scilit:
- The federated computer-aided control design systemIEEE Control Systems Magazine, 1982
- A VLSI RISCComputer, 1982
- Architecture of a Programmable Digital Signal ProcessorIEEE Transactions on Computers, 1982
- Compilers and Computer ArchitectureComputer, 1981
- Design Considerations for Single-Chip Computers of the FutureIEEE Transactions on Computers, 1980
- Decentralized parallel algorithms for matrix computationPublished by Association for Computing Machinery (ACM) ,1978
- Empirical evaluation of some features of instruction set processor architecturesCommunications of the ACM, 1977
- The FDP, a Fast Programmable Signal ProcessorIEEE Transactions on Computers, 1971
- The IBM System/360 Model 91: Machine Philosophy and Instruction-HandlingIBM Journal of Research and Development, 1967