Algorithmic bus and circuit layout for wafer-scale integration and multichip modules
- 31 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Towards a graphics/procedural environment for constructing VLSI module generatorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The technology of laser formed interactions for wafer scale integrationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A wafer scale visual-to-thermal converterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- MULGA-An Interactive Symbolic Layout System for the Design of Integrated CircuitsBell System Technical Journal, 1981
- Combining Graphics and a Layout Language in a Single Interactive SystemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981