Algorithm for VLSI chip floor plan
- 3 February 1983
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 19 (3) , 77-78
- https://doi.org/10.1049/el:19830055
Abstract
An algorithm for a VLSI chip floor plan is presented. It uses initial block placement obtained by the AR (attractive and repulsive force) method, and performs iterative block packing by gradually moving and reshaping blocks with chip boundary shrinking. By the use of several types of experimental data, it is shown that the method is very effective for handling various types of blocks and is well suited to interactive chip layout design.Keywords
This publication has 3 references indexed in Scilit:
- Automatic Placement of Rectangular Blocks with the Interconnection ChannelsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- Placement Algorithms for Arbitrarily Shaped BlocksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Methods for Hierarchical Automatic Layout of Custom LSI Circuit MasksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978