A new circuit configuration for a static memory cell with an area of 880 /spl mu/m/sup 2/
- 1 June 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (3) , 345-351
- https://doi.org/10.1109/JSSC.1978.1051051
Abstract
A new 5-transistor memory cell in double polysilicon technology with depletion-load elements and a minimum linewidth of 3 /spl mu/m is presented. The circuit configuration, based on a Schmitt trigger, leads to static memory cells having a bit density of 1100 bit/mm/SUP 2/ and an average power consumption of 5.5 /spl mu/W/cell. With the help of computer simulations the static and dynamic behavior of the basic circuit are calculated and discussed in detail as well as the two possible operation modes of the memory cell. These results compare favorably with the experimental results obtained on a realized 2/spl times/4 memory array. The performance of the proposed memory cell is the same as that of a conventional 6-transistor cell, but the area is reduced.Keywords
This publication has 1 reference indexed in Scilit:
- Two static 4K clocked and nonclocked RAM designsIEEE Journal of Solid-State Circuits, 1977