A Highly Stable Variable Time-Delay System
- 1 February 1953
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IRE
- Vol. 41 (2) , 228-235
- https://doi.org/10.1109/jrproc.1953.274210
Abstract
This paper describes a variable time-delay system having time jitter less than 0.00025 μsec, which is equivalent to 2.5 parts per million of its maxmum time delay. To achieve this stability, time delay in this system is accomplished exclusively by means of linear bilateral elements. A distributed amplifier is used to compensate the losses in the delay elements. Due to the fact that only a limited number of elements can be installed in a practical circuit, the signal pulse is permitted to travel through each delay element many times in order to increase the amount of total time delay. One of the experimental units having a total time delay up to 100 μsec in step of 1 μsec has been found to be satisfactory. The usual causes of time jitter in conventional time-delay circuits such as, variations of cut-off characteristics, noise, hum, and fluctuations of supply voltages, cannot affect the stability of this system. Practical circuits as well as experimental results are described.Keywords
This publication has 1 reference indexed in Scilit:
- Equalized Delay LinesProceedings of the IRE, 1946