Static-noise margin analysis of MOS SRAM cells
- 1 October 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (5) , 748-754
- https://doi.org/10.1109/jssc.1987.1052809
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Analysis of mesastable operation in RS CMOS flip-flopsIEEE Journal of Solid-State Circuits, 1987
- Ion-implanted thin polycrystalline-silicon high-value resistors for high-density poly-load static RAM applicationsIEEE Transactions on Electron Devices, 1985
- Stability and SER Analysis of Static RAM CellsIEEE Journal of Solid-State Circuits, 1985
- Worst-case static noise margin criteria for logic circuits and their mathematical equivalenceIEEE Journal of Solid-State Circuits, 1983
- Design consideration of a static memory cellIEEE Journal of Solid-State Circuits, 1983
- The behaviour of flip-flops used as synchronizers and prediction of their failure rateIEEE Journal of Solid-State Circuits, 1980