Three-dimensional distribution of CMOS latch-up current

1 April 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 8 (4) , 154-156
https://doi.org/10.1109/EDL.1987.26585

Abstract

This paper presents experimental evidence of relevant three-dimensional (3-D) effects in CMOS latch-up obtained by means of novel multicontact test structures. It is also shown that "quasi-" two-dimensional (2-D) experimental data in good agreement with numerical simulations can be achieved only by limiting the analysis to the central sections of wide experimental devices.

Keywords

CURRENT MEASUREMENT
CIRCUIT TESTING
NUMERICAL SIMULATION
CMOS TECHNOLOGY
SEMICONDUCTOR DEVICE MODELING
ANALYTICAL MODELS
SOLID MODELING
THYRISTORS
TWO DIMENSIONAL DISPLAYS
DOPING

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