Architecture and Performance of Radiation-Hardened 64-Bit SOS/MNOS Memory

1 January 1976

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 23 (6) , 1749-1755
https://doi.org/10.1109/tns.1976.4328573

Abstract

Realization of the 64-bit MNOS/SOS memory circuit demonstrates the feasibility of the design approach. Design techniques such as two-MNOS-transistors-per-bit cell, differential read circuitry and the implementation of PMOS resistive load static logic were used in the memory circuit to test their effectiveness and suitability for much larger nonvolatile radiation-hard memory arrays in SOS. We have shown that the 64-bit MNOS/SOS memory circuit can be successfully fabricated with tight uniformity uniformity of discrete device parameters. The MNOS transistors used in the circuit were processed to perform either as a RAM-type device or as an EAROM-type device. Also, discrete devices and the circuit have exhibited memory retention times in excess of three years. Additionally, we have verified that the circuit can survive total dose irradiation greater than 300K rads and maintain stored information after transient dose irradiation up to 1012 rad/sec.

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