A pulse-to-static conversion latch with a self-timed control circuit

This publication has 3 references indexed in Scilit:

• A 500 MHz 32-word X 64-bit 8-port Self-resetting CMOS Register File And Associated Dynamic-to-static Latch
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1997
• Circuit Design for CMOS VLSI
  Published by Springer Nature ,1992
• A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
  IEEE Journal of Solid-State Circuits, 1991