Sub-100ps experimental Josephson interferometer logic
- 1 January 1978
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper will cover experimental Josephson interferometer logic gates fabricated in a 5 μm technology with 1 μW/gate dissipation, citing measured delays of 40, 95 and 120ps for OR, AND and master slave latch, respectively.Keywords
This publication has 2 references indexed in Scilit:
- Quantum interference Josephson logic devicesApplied Physics Letters, 1975
- Fabrication of experimental Josephson tunneling circuitsJournal of Vacuum Science and Technology, 1974