Microprocessor Implementation Of A Linear Predictive Coder
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper describes a linear predictive coder (LPQ and its microprocessor fabrication. The LPC has an audio bandwidth of 3200 Hz, uses the autocorrelation formulation of LPC to determine the short term spectrum, and an Average Magni- tude Difference Function (AMDF) to extract pitch. A two multiplier/stage lattice filter at the receiver recreates the speech. The 2400 b/s full duplex LPC is implemented in the firmware of a horizontally coded microprocessor having a 48-bit instruction word and 16-bit data word. The processor architecture uses a 4-bit TTL ALU slice and a hardwared 16 x 16 bit parallel multiplier to rapidly process the data with relatively slow multiplication circuitry. With the chosen architecture, the LPC requires only 60 percent of the proces sor's capacity, while the processor itself has fewer than 150 integrated components. The low cost of the voice digitizer has resulted in commercial sales in a market that appears to be growing.Keywords
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