A VLSI layout for a pipelined Dadda multiplier
- 1 May 1983
- journal article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Computer Systems
- Vol. 1 (2) , 157-174
- https://doi.org/10.1145/357360.357366
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- The Area-Time Complexity of Binary MultiplicationJournal of the ACM, 1981
- The cube-connected cycles: a versatile network for parallel computationCommunications of the ACM, 1981
- Fixed-Point High-Speed Parallel Multipliers in VLSIPublished by Springer Nature ,1981
- Information transfer and area-time tradeoffs for VLSI multiplicationCommunications of the ACM, 1980
- Area-time complexity for VLSIPublished by Association for Computing Machinery (ACM) ,1979
- Two's Complement Pipeline MultipliersIEEE Transactions on Communications, 1976