Scaleable retrograde p-well CMOS technology

Abstract
The retrograde p-well CMOS technology utilizes a single high-energy boron implant to produce a self-aligned channel stop and an extremely shallow, low sheet-resistance p-well while maintaining controllable, low n-channel threshold voltages. Conventional CMOS technologies are limited by Gaussian profiles where surface concentration, sheet resistance, and junction depth are directly coupled and low threshold voltages require either deep junctions or high sheet resistance. The retrograde p-well peak charge resides 1µ below the surface which lowers npn-beta from conventional values of 500-1000 to 30- 50 and allows spacing between n- and p-channel devices to be reduced from 12-15µ to 3-6µ. This all-implanted CMOS technology has been developed, fully characterized and modeled for devices with electrical channel lengths below 2µ. Ring oscillators have, a 700psec. stage delay and a 1K RAM test structure shows a 3.7 times density improvement, lower latch-up susceptibility, lower defect density, and higher performance than the same RAM conventionally processed.

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