Design of a Power System Stabilizer Sensing Frequency Deviation
- 1 March 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Apparatus and Systems
- Vol. PAS-90 (2) , 707-713
- https://doi.org/10.1109/tpas.1971.293097
Abstract
A power system stabilizer specifically designed to the performance specifications of various utilities in the Western United States has been developed. The stabilizer utilizes synchronous machine terminal frequency as input. With this input signal, the stabilizing signal is derived using all static components and susceptibility to electrical noise is reduced. The design is modular with the sensing and signal conditioning elements implemented with all solid-state circuitry contained on draw-out printed circuit card assemblies. The design provides independent adjustment of gain and time constants with calibrated controls to allow direct settings from calculated data. Factory tests on the prototype verified its dynamic characteristics met or exceeded performance specifications. Field tests on a 422 MVA unit demonstrated improved damping of oscillations following switching of a tie line.Keywords
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