Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs
- 22 March 2004
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 25, 74-76
- https://doi.org/10.1109/iitc.2003.1219717
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabricationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Interconnect performance modeling for 3D integrated circuits with multiple Si layersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Interconnect limits on gigascale integration (GSI) in the 21st centuryProceedings of the IEEE, 2001