Quasi-static energy recovery logic and supply-clock generation circuits

1 January 1997

proceedings article
Published by Association for Computing Machinery (ACM)

p. 96-99
https://doi.org/10.1145/263272.263293

Abstract

A Quasi-Static Energy Recovery Logic family (QSERL) using two complementary sinusoidal supply clocks is proposed in this paper. A high-efficiency clock generation circuitry which generates two complementary sinusoidal clocks required by QSERL is also presented. The clock circuitry locks both frequency and phase of clock signals, which makes it possible to integrate adiabatic module into a VLSI system. We have designed an 8/spl times/8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 37% of energy over static CMOS multiplier at 100 MHz.

Keywords

SPICE SIMULATION
SPICE
SUPPLY-CLOCK GENERATION CIRCUIT
MULTIPLYING CIRCUITS
ADIABATIC MODULE
TWO PHASE SINUSOIDAL CLOCK
CLOCKS
CMOS LOGIC CIRCUITS
VLSI
CMOS CARRY-SAVE MULTIPLIER
100 MHZ
QUASI-STATIC ENERGY RECOVERY LOGIC
ENERGY RECOVERY

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