Optimization of self-aligned silicon MESFETs for VLSI at micron dimensions

1 January 1980

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 34-37
https://doi.org/10.1109/iedm.1980.189745

Abstract

This paper discusses the experimental optimization of the structural parameters of MESFET devices using a new self-aligned MESFET structure that incorporates a source-drain extension. Detail device characteristics as a function of gate length and width are presented. Ring oscillator measurements have demonstrated speed-power products as low as 1.5 femtoJoules.

Keywords

SILICON
MESFETS
VERY LARGE SCALE INTEGRATION
IMPLANTS
BORON
LABORATORIES
TAIL
METALLIZATION
INSTRUMENTS
STRUCTURAL ENGINEERING

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